1. Field of the Invention
The present invention relates to a method for an integrated circuit, and more particularly, to a method for determining a standard cell for an integrated circuit in the IC design flow.
2. Description of the Prior Art
Integrated circuits (IC) are often implemented by connecting together different types of functional blocks to achieve the desired IC specification. Please refer to FIG. 1. FIG. 1 is a block diagram of IC 10. The IC 10 includes logic blocks 12, memory 14, Input/Output (I/O) 16, analog/mixed signal blocks 18, and custom blocks 20. Some examples of analog/mixed signal blocks include functions of Phase Locked Loops (PLL) and Digital-Analog Converters (DAC). Of these, I/O 16, memory 14 and analog/mixed signal blocks 18 are typically used as a single pre-formed unit, or hard macro, by the IC designer, whereas some of the other blocks, primarily the logic, are constructed from a set of lower level sub-blocks, or standard cells, to enable a higher degree of customization and optimization.
An IC designer typically has numerous options to implement each of the functional blocks to create the best possible design for the IC. With respect to the I/O, memory and/or analog functions, hard macros that implement the required function but which are optimized for higher speed or lower power or smaller area are available, and the IC designer chooses the hard macro best suited to the particular design.
Implementing logic functions is much more complex due to the typically large number of standard cells, ranging from tens of thousands to tens of millions, needed to implement the logic functions. Each standard cell is comprised of a predetermined number of transistors coupled together to perform a particular logic function. For example, there are standard cells that perform the functions of NAND, AND, NOR and OR gates, as well as more complicated logic functions such as single bit adders. The IC designer typically has access to different implementations of these low level functions, the different implementations targeted respectively for lower power, higher speed or smaller area. Electronics design automation (EDA) tools are necessary to analyze various implementations and obtain an optimum result when designing complex logic functions.
Please refer to FIG. 2. FIG. 2 is a flowchart of IC design according to the prior art. Steps of the IC design are as follows.
Step 110: design RTL (register transfer level), the IC designer programs register transfer level code to describe a logic function requirement of the circuit so as to generate a RTL file;
Step 120: synthesis, using synthesis software to verify the RTL file generated in the step 110; the synthesis software is coupled to a library of standard cells; a typical known standard cell library includes a plurality of different cell types, such as AND, NOR, flip-flop and inverter cells, and each cell will be available in several different sizes; the synthesis software analyzes the logic function of the RTL file with an implementation of that function using various types of standard cells that meet the specification;
Step 130: APR (auto place and route), the EDA tool can place and route standard cells for the RTL file that has passed the verification of the synthesis software in the step 120; after APR, a netlist is generated including a list of cells required and the necessary connections between them; in addition, the IC designer can choose a suitable standard cell for the IC according to the area constraint and timing constraint;
Step 140: layout, the placement tool uses the information from the library to place the cells so as to minimize the interconnections required by the netlist; a router then draws the wiring between the placed cells to implement the connectivity specified in the netlist so as to complete the layout.
In general, each cell will be available in several different sizes, the size referring to the size of the output driver transistors. Although the selection of the correctly sized cell is driven by the design, it is unavoidable that a larger cell (larger output driver transistors) will have a greater delay than a smaller cell.
One optimization target for IC design is cost. A smaller area logic circuit will allow a larger number of usable ICs per silicon wafer, reducing the cost of each IC. The IC designer's goal is to design the IC so that the specifications are met using the smallest possible silicon area. The IC designer is typically provided with multiple variants of each hard macro, the variants showing different trade-offs among the variables of area, speed and power. This extends to standard cells where each logic function, for example an AND gate, has multiple different implementations, the different implementations required for different output drive strength. Standard cells with increased drive strength are typically larger than those with relatively less output drive strength. IC design according to the prior art focus on the cost, so the IC design flow mainly assists IC designers to create the smallest implementation of an IC incorporating the various logic function blocks. However, when the IC designer requires designing a circuit of a higher performance and stability, they do not have any reference information.